This invention relates generally to the field of integrated circuit manufacturing, and more specifically to methods for improving the planarization of a wafer when using Chemical Mechanical Polishing.
Moore""s Law, which is named after Gordon Moore, the founder of Intel Corporation, states that the speed and density of computers will double every 18-24 months. A corollary to Moore""s Law is that the size of the transistors and other features used in integrated circuits will shrink by a factor of two every 18-24 months. For the most part, Moore""s Law has held true since the early days of the microprocessor.
As the feature sizes decrease and the number of devices increase, the number of the interconnect lines must also increase. To accommodate the increasing number of interconnect lines, many manufacturing processes allow several metal interconnect layers. When providing more metal interconnect layers, the surface topology of each layer becomes increasingly important. It is known that adverse surface topologies may reduce the reliability or current carrying capabilities of a subsequently deposited metal layer, particularly near xe2x80x9cstepsxe2x80x9d on the surface. Adverse surface topologies also tend to prevent minimum features sizes from being formed on subsequent layers because the optics used by many photolithography systems to create minimum feature sizes do not have a sufficient depth of field to properly focus on the various undulations in the non-planar surface.
Various planarization techniques have been developed to improve the surface topology of selected layers. Early techniques for planarization included reflow and etchback. Reflow involves the use of an oxide layer such as borophosphosilicate glass (BPSG), which is deposited over a patterned layer of the wafer and then heated. Heating the BPSG causes the BPSG to melt, which then forms a relatively planar top surface on which a subsequent metal layer may be deposited. A limitation of this technique is that the melted BPSG often does not sufficiently planarize the surface, particularly when subsequent layers include small feature sizes such as submicron features sizes.
Like reflow, etchback involves the use of a thick oxide deposited over a patterned metal layer. However, rather than melting the oxide layer, a thick layer of photoresist is deposited on top of the oxide layer, and the wafer is placed in a plasma etch system. The plasma etch system is set so that the etch rates for the oxide and the photoresist are nearly identical. The wafer is then etched until all of the photoresist is removed, which also removes the higher regions of the oxide layer. The cycle is repeated if necessary. A limitation of this technique is that the etching process often follows the surface topology of the resist layer, which is not completely planar. Thus, etchback tends to only smooth out the steps.
A more recently developed technique is called Chemical Mechanical Polishing (CMP). CMP involves the deposition of a thick dielectric layer, which is often chemically deposited in a reactor using heat and/or RF or spun on the wafer and cured to remove trapped organics, or a combination of both. The wafer is then chemically and mechanically polished using a polishing pad, which uses a slurry of abrasives and one or more etching agents.
A limitation of CMP is that the degree of planarization is often dependent on the topography of the underlying patterned layer. For example, variations in topography can cause local variations in pressure on the polishing pad. High areas that have small underlying feature dimensions tend to exert a greater mechanical pressure on the polishing pad than high areas that have relatively large underlying feature dimensions. Accordingly, the high areas that have small underlying feature dimensions tend to be removed more quickly than those areas that have larger underlying feature dimensions. As a result, the amount of material that is removed during the CMP process tends to vary over the surface of the wafer, resulting in undesirable variations in surface topography.
A need exists, therefore, for an improved method of CMP planarization that reduces the variations in the resultant surface topography due to variations in the topography of the underlying layers.
The present invention overcomes many of the disadvantages of the prior art by providing an improved method of CMP planarization that reduces variations in the resultant surface topography due to variations in the topography of the underlying layers. The improved method adds only a minimum number of additional processing steps such that wafer costs remain low.
In a preferred embodiment, the present invention provides a method for improving the planarization of a top layer that is deposited over a patterned layer on a semiconductor wafer. The patterned layer may include both small and larger features. In accordance with the present invention, openings, grooves, or trenches are etched partially or completely through certain large target features in the patterned layer in an effort to mimic the topography of areas where the patterned layer includes smaller features. This may reduce the variations in the topography of the patterned layer so that when a top layer is provided over the patterned layer, all of the high areas of the top layer will be removed at similar rates by the polishing pad of a CMP system. Preferably, the target features are relatively large feature such as a bonding pad, power bus, polysilicon capacitor, ESD diode, etc.
In one illustrative method of the present invention, a first layer of photoresist is deposited on top of an unpatterned underlying metal, oxide, poly or other layer. The layer of photoresist is patterned twice using two different masks. During a first exposure, the layer of photoresist is exposed using a first mask for a first predetermined time. The first predetermined time is preferably sufficient to develop the photoresist layer from front to back. The first mask can be used to define a pattern in the underlying layer, which may be required for circuit functionality. Then, and before developing the photoresist, the photoresist layer is exposed using a second mask for a shorter duration of time so that the pattern defined by the second mask is not developed entirely through the photoresist layer. The second mask can be used to define a pattern for partially etching the at least one opening, groove, or trench in the target features.
The photoresist layer is then developed, which removes all of those portions exposed using the first mask and only part of the those portions exposed using the second mask. The top surface of the wafer is then exposed to an etchant. The etchant is selected to etch both the remaining photoresist as well as the exposed underlying layer at some predefined selectivity, preferably at similar rates. Thus, in those areas where some photoresist remains, the etchant must first etch through the photoresist before etching the underlying metal layer. Accordingly, the at least one groove, trench, or opening in the target features are etched to a depth typically less than the depth of the patterned underlying layer (e.g. one-half the thickness of the underlying oxide, metal, poly or other underlying layer). A top layer is then provided on the patterned layer, and the top layer is planarized using a conventional CMP process.
In another illustrative method of the present invention, and prior to etching the at least one opening, trench, or groove, a first layer of photoresist is deposited on top of the unpatterned underlying layer. The layer of photoresist is patterned by exposing the layer of photoresist during a photolithogaphy process using a first mask for a predetermined duration of time. After the first layer of photoresist is developed, a pattern is etched a pre-determined depth into the underlying layer of material. In one embodiment, the first mask is used to define the pattern that is required for circuit functionality or operation. The remaining photoresist is then removed, and a second layer of photoresist is provided on top of the patterned layer and exposed during a second photolithography process using a second mask for a pre-determined duration of time. The second layer of photoresist may define a pattern for etching the at least one opening, groove, or trench in the target features of the patterned layer. After the second layer of photoresist is developed, the at least one groove, trench, or opening is etched a predetermined depth into the target features. The at least one groove, trench or opening may be etched only part way through the underlying layer, or all the way through as desired. A top layer is then provided on the patterned layer. Finally, the top layer is planarized using a conventional CMP process.
In another illustrative embodiment of the present invention, a single mask is used to define both the pattern in the underlying material that is required for circuit functionality and the at least one opening, groove, or trench in selected target features. The mask is a conventional photolithography mask that has been designed to define at least one opening, groove, or trench in selected target features. This may provide more consistent surface topology across the surface of the wafer.
Other objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein:
FIG. 1 is a schematic representation of a typical CMP system;
FIG. 2 is a cross-sectional representation of a wafer containing a substrate layer, patterned metal layer, and an Inter Layer Dielectric (ILD);
FIG. 3 is a cross-sectional representation of the wafer shown in FIG. 2 placed adjacent to a polishing pad of a CMP system;
FIG. 4 is a flow diagram of a typical metal deposition, metal etch, ILD deposition, and CMP process;
FIGS. 5A-5D are the cross-sectional wafer representations of the process of FIG. 4;
FIG. 6 is a flow diagram of an illustrative metal deposition, metal etch, ILD deposition, and CMP process in accordance with the present invention;
FIGS. 7A-7D are cross-sectional wafer representations of the illustrative process of FIG. 6;
FIG. 8 is a flow diagram of another illustrative metal etch and CMP process in accordance with the present invention;
FIG. 9 is a flow diagram of an illustrative method for forming a damascene structure with a CMP planarization process in accordance with the present invention;
FIGS. 10A-10D are cross-sectional wafer representations of the illustrative process of FIG. 9;
FIGS. 11A-11B represent a top view and a cross-section view, respectively, of a spiral metal bonding pad;
FIGS. 12A-12B represent a top view and a cross-section view, respectively, of a grooved metal bonding pad having a number of openings formed therein;
FIGS. 13A-13B represent a top view and a cross-section view, respectively, of a longitudinally grooved metal bonding pad;
FIG. 14 is a top view of a mask for a layer including at least one bonding pad;
FIG. 15 is a top view of a mask for a layer including at least one large area capacitor; and
FIG. 16 is a top view of a mask for a layer including at least one power bus.